Continuing on from Saturday 30 June, 1-5PM: FPGA Workshop #1 - build & simulate a RISC CPU design as per FPGA meetup/workshop with @sjdavies 
(Stephen please add more info here about what folks will need to bring along, and what they’ll be doing
Hi all,
all workshop materials are available online at Github.
In workshop #2 we will be looking to add a register file and a control ROM to our design. With these components in place we can then start executing complete instructions. Right now this will be limited to 3 instructions, no-operation (NOP), load immediate (LDI) and logical and (AND).
To understand the register file we are going to need to know about sequential logic. This means learning about flip-flops and state machines.
To make sense of what I’ve mentioned above I will talk a little about RISC instruction sets, instruction formats and the AVR instruction set.
What you need to bring:
- A laptop or computer with Xilinx Vivado installed
- Warm clothing, the space can get chilly this time of year
If you missed workshop #1 you are welcome to attend. You’ll need to work through Labs 2-5 before attending. I have posted solutions in the code section of the repository so reading through should be enough to get you up to date. Last sessions lecture slides are available as a PDF.
See you there!
Stephen
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Hi all,
a quick reminder that the workshop happens this Saturday. Am looking forward to seeing you there.
Cheers,
Stephen
The committee meeting is running before hand so the the space should be open, if not I should be there so I can unlock the door.
Ok, thanks.
I am installing the software, but I see that the Xilinx site has an “Update 1” of the packages. Any idea how to use it? Ignore it?
[later] Figured it now (I use the linux version).
1 extract the archive (Xilinx_Vivado_SDx_Update_2018.2.1_0726_1815.tar.gz)
2 enter the new directory (Xilinx_Vivado_SDx_Update_2018.2.1_0726_1815)
3 run ‘./xsetup’
I actually did not have enough room on the VM (extracted size is 6.4GB) so I extracted on my home server and net mounted it in the VM. It updated without a problem.
Free space remained about the same (20MB less).
In case anyone needs to know: I created a 40GB disk (/ is 37GB) and after installing ubuntu 16.04.3LTS and vivado (web install) I see 33GB used (1.8GB free for users). A bit tight but may be OK.
… so I have been working on completing workshop #2 based on Stephen’s excellent doco.
For me slow process, lots of revision, reading reference material, help etc. So far the doco has proved to be spot on. For example had a lot of trouble with “mark as top”, but that was not appearing because of error in my code. Now got to the point where recommended computer specs are proven correct, so far 5 hours compiling the register file on this old laptop.
Only bone I can pick is the temperature - here the minimums are 27/28/29 and stays hotter inside until the air con kicks in!
Mostly though, I feel like I am gathering the processes and syntax together, just need a lot more practice and do some my own code…
Thanks,
@sjdavies
Hi Spencer,
Saturdays session went well. Glad to hear you’ve been able to follow along.
When you feel you ‘get’ how the control ROM does its thing I suggest looking into how to add the following instructions:
Logical AND Immediate (andi)
Logical OR (or)
Logical OR Immediate (ori)
Logical XOR (eor)
Clear Register (clr) (just a special case of eor where Rd = Rr)
Move Register (mov)
The spreadsheet in /docs provides more detail. Only the control ROM needs to change. The ALU already has the xor/or functions. No datapath changes are required.
Cheers,
SteveD
OK, thanks & will do … although after yet another 2 hours of still compiling, might have to wait until I return to a faster computer.
Meanwhile, reading & notes…
Glad to hear last session went well, was sorry could not be there…already looking forward to next one.